期刊名称:International Journal of Electronics Communication and Computer Engineering
印刷版ISSN:2249-071X
电子版ISSN:2278-4209
出版年度:2012
卷号:3
期号:6
页码:1532-1536
出版社:IJECCE
摘要:VHDL programming for IEEE single precision floating point multiplier module have been explored because floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed. Floating point operations are hard to implement on FPGAs i.e. on reconfigurable hardware’s because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations. The parameter number of bonded IOBs (Input Output Blocks) has been analyzed while implementing the floating point multiplier on Spartan 2, Spartan 2E, Spartan 3 and Spartan 3E FPGA’s.
关键词:Floating Point Multiplier; FPGAs; Memory; Xilinx and Spartan