文章基本信息

标题：Computational Reduction Logic for Adders
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作者：M. Siva Kumar ; Dr.S.K.Srivatsa
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2013
卷号：1
期号：3
出版社：S&S Publications
摘要：As the technology is increasing, the designer is trying to increase the density of chips, decrease the power consumption and power dissipation, decrease the area and increase the computational and storage logics on single chip by maintaining lower complexity. But there is no single approach till no w h aving following ideal outputs. When complexity of computational logic increases, the designing, testing, debugging becomes even more co mplex. So this paper gives a different approach of any n-bit adder using less computations, Look up tables, Slices and gates, which is verified and simulated in Xilinx ISE DESIGN SUITE 14.2 (Verilog Hardware Descriptive Language) and Cadence .In general we use carry look ahead adder for adding the two numbers along with carry . But this is not applicable because when we consider a large number of bits, complexity increases. So this paper gives an alternative for decreasing co mplexity and the memory.
关键词：Look Up tables; Slices; Carry Look Ahead adder