文章基本信息

标题：Clock Gated Single-Edge-Triggered Flip-Flop Design with Improved Power for Low Data Activity Applications
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作者：mran Ahmed Khan ; Mirza Tariq Beg
期刊名称：International Journal on Electrical Engineering and Informatics
印刷版ISSN：2085-6830
出版年度：2014
卷号：6
期号：3
DOI：10.15676/ijeei.2014.6.3.9
出版社：School of Electrical Engineering and Informatics
摘要：In this paper, the proposed flip-flop reduces power consumption by reducing theclock switching power that was wasted otherwise. Unlike many other gated flip-flops, theproposed gated flip-flop has state retention property to save power and to switch circuitbetween idle and active modes smoothly. The feedback path is also improved in theproposed flip-flop to decrease power dissipation. The proposed clock-gating scheme onlyrequires 4 transistors, thus occupies the small silicon area. Further, the proposed clock gatingnetwork can be shared among a group of flip-flops to reduce the power and area overheadof the gating network. The simulation results show that for all supply voltages, the proposedflip-flop has the least power dissipation among all the designs for low switching activities.The proposed flip-flop has up to 7.82 times power improvement than the existing flip-flops.However, for 100% data activity, the proposed FF consumes up to 2.71 times power thanthe existing flip-flops. The proposed clock gated flip-flop structure is best suited forapplications where input signal switching activity is low and speed is not a crucial factor
关键词：Low power; CMOS digital integrated circuits; transition probability; edge;triggered; storage element; VLSI