文章基本信息

标题：Comparative Study of Delay and Power Dissipation of a Low Power CMOS BPSK Modulator Circuit
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作者：Sayani Palit ; Madhumita Mukherjee
期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2014
卷号：4
期号：1
页码：208-211
出版社：International Journal of Soft Computing & Engineering
摘要：In this paper we have presented a BPSK modulator using low power CMOS technology. The key design issues in VLSI circuit design are power and delay. Thus in this paper we have focused on LP CMOS with different technologies(16nm, 22nm ,32nm,and 45nm) with the help of TANNER EDA Tool. The value of model parameters are used from Predictive Technology Model(PTM). The T-SPICE simulation results indicate that there is a 59% deduction in Dynamic power For 16nm technology compare to 45nm technology keeping supply voltage constant whereas there is 74.64% reduction in power delay product in 16nm technology compare to 45nm technology
关键词：BPSK; LP CMOS; Power dissipation; PTM