文章基本信息

标题：Study and Analysis of Universal Gates Using Stacking Low Power Technique
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作者：Neha Goyal ; Renu Singla ; Puneet Goyal 等
期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2014
卷号：5
期号：3
页码：4200-4204
出版社：TechScience Publications
摘要：The main objective of this paper is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, this work focuses on the reduction of the power dissipation, which is showing an ever-increasing growth with the scaling down of the technologies. Various techniques at the different levels of the design process have been implemented to reduce the power dissipation at the circuit, architectural and system level. Conventional NAND gate and Nor gate are designed snd then compared with the stack NAND and stack NOR using 180nm technology.
关键词：power; transistors; delay; CMOS; NAND Gate;NOR Gate; stacking; TANNER Tool; conventional