文章基本信息

标题：Architectural Design Issues in a Clockless 32-Bit Processor Using an Asynchronous HDL
本地全文：下载
作者：Oh, Myeong-Hoon ; Kim, Young Woo ; Kwak, Sanghoon 等
期刊名称：ETRI Journal
印刷版ISSN：1225-6463
电子版ISSN：2233-7326
出版年度：2013
卷号：35
期号：3
页码：480-490
DOI：10.4218/etrij.13.0112.0598
语种：English
出版社：Electronics and Telecommunications Research Institute
摘要：As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13- CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 /MHz and is comparable to that of a synchronous counterpart.
关键词：Clockless processor;asynchronous circuit;asynchronous HDL;mircoarchitecture;EISC;TiDE;Haste