文章基本信息

标题：Modification of Instruction Set Architecture in a UTeMRISCII Processor
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作者：Ahmad Jamal Salim ; Nur Raihana Samsudin ; Sani Irwan Md Salim 等
期刊名称：International Journal of Computer Trends and Technology
电子版ISSN：2231-2803
出版年度：2013
卷号：4
期号：5-3
出版社：Seventh Sense Research Group
摘要：The development of application specific instruction set processor (ASIP) is a methodology in designing the processor system. The designing of processor system is focused on the internal architecture of the processor. By using the ASIP design, it can offer the optimum performance and also the flexibility in a processor architecture, but with limited application. However, by implementing the processor on Field Programmable Gate Array (FPGA), it could further extend the opportunity to reconfigure the architecture instantly. Therefore, this paper is about the implementation of the modification of a 16bit wide instruction set for a simple 8bit softcore RISC processor called UTeMRISCII. The purpose of the project is to improve the ability of the processor by adding a new instruction set that can be able to perform basic digital signal processing (DSP) algorithm. For verification, a multiplyaccumulate (MAC) instruction is created as the new customized instruction. The modification of the instruction set architecture is achieved by using Hardware Description Language (HDL) implementation. To validate the operation of new customized instruction in the software platform, the CPUSim software is used as the simulator to observe the output. Meanwhile, in the hardware platform, the new customized instruction is translated into processor design and verified using the Xilinx ISE software. The Xilinx Virtex6 board is used to implement the processor. The simulation and hardware synthesis results proved that the new MAC instruction implementation performed correctly and produces correct outputs during the processor execution.
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