文章基本信息

标题：A FPGA Stereo Matching Algorithm Modeled By DSP Builder
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作者：Zhang, Xiang ; Chen, Zhang wei
期刊名称：Journal of Computers
印刷版ISSN：1796-203X
出版年度：2014
卷号：9
期号：10
页码：2359-2364
DOI：10.4304/jcp.9.10.2359-2364
语种：English
出版社：Academy Publisher
摘要：This paper proposes a System-on-Programmable-Chip (SoPC) architecture to implement a stereo matching algorithm based on the sum of absolute differences (SAD) in a FPGA chip which can provide 1396×1110 disparity maps at 30 fps speed. The hardware implementation involves a 32-bit Nios II microprocessor, memory interfaces and stereo matching algorithm circuit module. The stereo matching algorithm core is modeled by the Matlab-based DSP Builder. The system can process many different sizes of stereo pair images through a configuration interface. The maximum horizon resolution of stereo images is 2048.
关键词：Stereo matching; System-on-programmable-chip; FPGA; Disparity map; SAD; DSP Builder