文章基本信息

标题：An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation
本地全文：下载
作者：Yoshinobu Higami ; Kewal K. Saluja ; Hiroshi Takahashi 等
期刊名称：Information and Media Technologies
电子版ISSN：1881-0896
出版年度：2009
卷号：4
期号：4
页码：727-739
DOI：10.11185/imt.4.727
出版社：Information and Media Technologies Editorial Board
摘要：Conventional stuck-at fault model is no longer sufficient to deal with the problems of nanometer geometries in modern Large Scale Integrated Circuits (LSIs). Test and diagnosis for transistor defects are required. In this paper we propose a fault diagnosis method for transistor shorts in combinational and full-scan circuits that are described at gale level design. Since it is difficult to describe the precise behavior of faulty transistors, we define two types of transistor short models by focusing on the output values of the corresponding faulty gate. Some of the salient features of the proposed diagnosis method are 1) it uses only gate-level simulation and does not use transistor-level simulation like SPICE, 2) it uses conventional stuck-at fault simulator yet it is able to handle transistor shorts, thus suitable for large circuits, and 3) it is efficient and accurate. We apply our method to ISCAS benchmark circuits to demonstrate the effectiveness of our method.