文章基本信息

标题：Architecture Approach for Scalable Encryption Algorithm and Implementation in FPGA
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作者：K.Rajasekhar ; S.Adilakshmi ; Dr. Fazal Noorbasha 等
期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2012
卷号：3
期号：2
页码：434-438
语种：English
出版社：Ayushmaan Technologies
摘要：Most present symmetric encryption algorithms result from a tradeoff between implementation cost and resulting performances. In addition, they generally aim to be implemented efficiently on a large variety of platforms. Most present symmetric encryption algorithms result from a tradeoff between implementation cost and resulting performances. In addition, they generally aim to be implemented efficiently on a large variety of platforms. Scalable encryption algorithm is targeted for small-embedded application with limited resources (such as memory size, processor capacity). SEA n, b is parametric in the text, key and processor word size and uses a limited instruction set (i.e. NOT, AND, OR, XOR gates, word rotation and modular addition). And it has a provable security against linear and differential cryptanalysis. This paper includes the conversion of loop of SEA into architecture. in such a way that encryption and decryption process are separated, loop is split into two parts and controlling inputs are removed. By this method it is easy to design in VHDL language, for implementation in FPGA.