文章基本信息

标题：Estimation of leakage power and delay in CMOS circuits using parametric variation
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作者：Preeti Verma ; Preeti Verma ; Ajay K. Sharma 等
期刊名称：Perspectives in Science
印刷版ISSN：2213-0209
电子版ISSN：2213-0209
出版年度：2016
卷号：8
页码：760-763
DOI：10.1016/j.pisc.2016.06.081
语种：English
出版社：Elsevier
摘要：Summary With the advent of deep-submicron technologies, leakage power dissipation is a major concern for scaling down portable devices that have burst-mode type integrated circuits. In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor) is discussed. Using high threshold transistors at the place of low threshold leakage control transistors, result in more leakage power reduction as compared to LCT (leakage control transistor) technique but at the scarifies of area and delay. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. It is found that the leakage power dissipation increases with increasing temperature, supply voltage and aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum peak of equivalent output noise is obtained as 127.531nV/Sqrt(Hz) at 400mHz.
关键词：Leakage current; Aspect ratio; Transistor stacking; LCT; Deep submicron;