文章基本信息

标题：Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs
其他标题：Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs
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作者：Yasuaki Ito ; Koji Nakano
期刊名称：International Journal of Networking and Computing
印刷版ISSN：2185-2847
出版年度：2011
卷号：1
期号：1
页码：49-62
语种：English
出版社：International Journal of Networking and Computing
摘要：Consider the following operation on an arbitrary positive number: if the number is even, divide it by two, and if the number is odd, triple it and add one. The Collatz conjecture asserts that, starting from any positive number m, repeated iteration of the operations eventually produces the value 1. The main contribution of this paper is to present an efficient implementation of a coprocessor that performs the exhaustive search to verify the Collatz conjecture using a Xilinx Virtex-6 FPGA with DSP blocks, each of which contains one multiplier and one adder. The experimental results show that, our coprocessor can verify 4.99Ã—108 64-bit numbers per second. Also, we have implemented a multi-coprocessors system that has 380 coprocessors on the FPGA. The experimental results show that our multi-coprocessor system can verify 1.64Ã—1011 64-bit numbers per second.
关键词：Hardware Algorithm; Collatz conjecture; FPGA Implementation; DSP blocks; Block RAMs